PowerDRC/LVS 2.2.1 released
Kiev, Ukraine, June 17 2016

POLYTEDA LLC, a provider of semiconductor design software and PV-services, today announced the general availability of PowerDRC/LVS version 2.2.1
This release is dedicated to hierarchical processing of cell arrays and standard cells to dramatically improve performance in multi-CPU mode. Beside of this:

  • Added support of number and string variables in PWRL along with conditional directives #if / #else

  • Added preprocessor directives #define, #ifdef, #ifndef for conditional rule compilation

  • Added $overunder and $underover options to $size

  • Added an example of using parameters extraction for the assessment of parasitic capacitances

  • Added support of extraction devices by nets
  • Added a lot of minor improvements for integration with Cadence Virtuoso
PowerDRC/LVS is designed to process integrated circuit (IC) designs of various size at technology nodes up to 40nm, with run times which are fast and completely predictable. It is massively scalable and provides turnaround is time that is up to an order of magnitude faster than existing solutions. PowerDRC/LVS achieves this scalability and turnaround time through the use of a unique data structure and native window scanning technique.

Production Quality

During beta test period, POLYTEDA worked with wide list of partners and evaluators in Europe and US to validate accuracy and performance for production on real designs.

Foundry Support

Contact us to learn more about the availability of foundry rule decks.


The release version is officially available from POLYTEDA. Contact sales@polyteda.com for more details.


POLYTEDA LLC is a rapidly growing EDA company focused on providing fast, accurate and affordable verification solutions for electronic design companies. For more information about POLYTEDA and its products, please visit www.polyteda.com.