Advanced physical verification solutions
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    Un-compromising accuracy for all checks—simple and complex!
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    Multi-CPU operations for linear performance gain on a single host, LSF, SGE, NEFELUS cloud
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    Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm
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    High performance, delivering maximum CPU efficiency per rule check
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    Fastest and most accurate flat engine DRC on the EDA market
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    Scalability proven on 2, 4, 6, 8, 12, 16, 24, 32 CPUs
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    PowerDRC/LVS is available on NEFELUS Cloud Platform as pay-per-use service
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    Functional completeness

Q: Where does PowerDRC fit in a daily development flow?

А: PowerDRC/LVS may be used for daily work on all stages of chip development and debugging – from library cells/blocks to assembly to top cell verification.

PowerDRC/LVS includes components that provide DRC, LVS, XOR, QuickDiff and Fill generation as well as GUI cockpit for running verification and interactive debugging, and Short Finder utility to locate and visualize shorted nets.

Q: Can I use PowerDRC/LVS from any popular design environment?

A: Sure. With special kit provided with its installation package, PowerDRC/LVS provides interoperability with Cadence IC5.x, IC61, SpringSoft Laker, and free KLayout viewer/editor, so that you can run PowerDRC/LVS from your layout editor and then get violations visualized in your preferred environment. Besides this PowerDRC/LVS support integration with AWR Analog Office and LVS cross-probbing for Symica DE.

Q: Does PowerDRC/LVS have a GUI of its own?

А: You can run PowerDRC/LVS from the command line, or run any component of the suite from PowerRDE GUI cockpit, or use the GUI to browse the results of previous command line runs.

Q: Can I verify my 32 and 28 nanometer chips with PowerDRC/LVS?

А: Mostly yes. Yet to make sure if some specific rules for these advanced nodes may be checked we would need additional information including DRM and (sometimes) Process Specification.

Q: I have a very hierarchical layout. Will it be processed faster?

А: PowerDRC/LVS supports hierarchical macroblocks recognition for DRC in multi-CPU mode and hierarchical extraction in LVS. So you can get notable (actually manifold) acceleration if you will follow our recommendations on preparation of your LVS netlist, layout, and rules.

Q: My layout consists of 80-90 percent cell array(memory). Will it be processed faster?

А: Yes. In DRC, you should first check the cell array interface separately, and proceed to final checking of the top cell with the entire matrix only once you have your chip debugged on the lower levels.

In LVS, you only need to use special option, which tells the program to recognize memory cells as hierarchical units during extraction.

Q: What formats of input and output data are supported in PowerDRC/LVS?

А: It is GDSII and OASIS for layout and CDL, SPICE, Verilog for schematic. OpenAccess for schematic and layout is only supported in integration with Cadence IC61 through their built-in convertor.

Q: Can I re-use my rules to work with PowerDRC/LVS?

А: PowerDRC/LVS doesn’t work natively with Calibre or Assura rule files. However, PWRL rule language of PowerDRC/LVS was intentionally made close to SVRF in its semantics and syntax just to facilitate migration. Still they are different, and certain functional capabilities of PWRL are missing in SVRF. For example, there are means that let user optimize the process of verification, like block command. Some complicated checks that require dozens of lines in other languages take as few as couple lines in PWRL.


Accuracy

Q: Why should I trust correctness and accuracy of PowerDRC/LVS verification?

А: PowerDRC/LVS was certified by UMC for 180, 65, and 40 nanometers, by IHP for 250 and 130 nanometers, as well as for many other technologies with silicon-proven designs (more than 10 permanent customers).

Q: I have an uncommon specific layout file with circles and the like. Would that impact accuracy of verification with PowerDRC/LVS in any way? Any pitfalls to be aware of?

А: No, we do not expect problems in such cases. Circles are approximated with polygons, and PowerDRC/LVS supports any-angle operations. False violations common in approximation may be prevented by proper adjustment of tolerance.


Performance

Q: Can I speed up verification by using a multi-core CPU system or by adding more RAM modules?

A: Yes, you can. Our tool can perform DRC verification in multi-CPU mode engaging as many available CPU cores as your license and hardware allows. Specific acceleration depends on details of your design and the quality of rules. Multi-CPU mode is not supported for LVS.

More RAM will not give better performance by itself but it may be useful in multi-CPU mode. Minimal RAM needed to run PowerDRC/LVS is 1GB, and recommended is 8GB.

Q: Can I speed up DRC verification by using a multi-host system?

A: Yes, you can. PowerDRC in multi-CPU mode readily runs in SGE and LSF grid, as well as in NEFELUS cloud environment (www.nefelus.com). When verifying a SRAM memory chip on 32-core system in the cloud we got up to 27x acceleration cp single CPU system.

Q: Can I speed up verification by using a GPU?

A: Unfortunately, GPU-accelaration isn’t supported in the current version of PowerDRC/LVS.

Q: So, how fast is PowerDRC/LVS compared to competing tools?

А: On the average, PowerDRC/LVS is twice as fast as Calibre and 5-6x faster than Assura in single host mode on same design, hardware and OS. It definitely benefits from having the fastest flat engine on the market under the hood.


Market positioning and licensing

Q: What is your license policy?

А: Fairly flexible. Most of our customers acquire one-year license for certain number of cores, with technical support. Longer licenses, say for 3 years, come with considerable discount. Some customers don’t need verification services for that long, and we cut quarterly or even monthly licenses for them. If you want yet more flexibility then you could access PowerDRC/LVS through NEFELUS cloud services with payments on Pay-Per-Use basis.

Q: What is your clientele? Where can I read a review of your product?

А: Our customers are among small and medium companies working on technologies up to 40 nanometers and looking for a cheaper physical verification tool yet not at the expense of quality and accuracy. IHP, Vivid Engineering, Genesys Ltd have been using PowerDRC/LVS for more than 5 years, various customers of AWR Corp (SIEMENS AG, DSTO, etc. ) – for more than 4 years. We are planning to present their opinions on the product at our website in the nearest future.


    Technical support and additional services

Q: If I find an issue in your product how quickly I can get the issue resolved?

А: Our policy is to have quarterly releases. So if yours is a minor or trivial bug then you will get it fixed with new version provided you subscribed for technical support. More sophisticated bugs especially ones blocking your work will be addressed immediately, and you will get hot fix version right once it is fixed. Fortunately, such cases are exceptionally rare and the technical support team will do their best to suggest a workaround in the interim.

Q: How painful is the process of migration to PowerDRC/LVS provided Calibre or Assura technical files are available?

А: PowerDRC/LVS is really easy to start working with. The effort needed to convert your rules depends on their particular technology and total number. You can try to do that yourself or we can do that for you along with optimization for better performance.

Q: I cannot write or customize my rule deck set. Can you help with that for your product?

А: Yes, we can. For that we need DRM, the rules you use with your current tool, and your readiness to communicate online on a regular basis. We usually add the price for this service to technical support.

Q: How can I get hand-on experience with PowerDRC/LVS?

А: Just fill in a request at POLYTEDA web site. We usually provide the latest version of the product along with 1-month free trial license. To get most of it you will need to sign NDA and share your data with us so that we could convert your rule files before you start your evaluation.