POLYTEDA

Fastest & most accurate DRC technology and cloud-ready PV-flow
Capabilities
PowerDRC/LVS
  • The main mission is to speed up the process of PV by using One-Shot™ processing that delivers maximum hardware efficiency (CPU, RAM, cache) per one rule check
  • Many times silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm
  • More accurate then competitors due to using native flat DRC engine
  • Extremely predictable performance and behavior (key feature for PV)
  • Proven multi-CPU scalability (up to 64x CPUs)
  • Cloud-proven
PowerRDE
PowerRDE is a GUI application that allows user to create DRC, LVS or XOR run configuration, save it in a run configuration file (RCF), read a saved configuration, run PowerDRC/LVS, view run progress, review results, debug violations, etc.

PowerRDE allows to run PowerDRC/LVS in multi-CPU mode on a single host or multiple hosts controlled by Platform LSF and Oracle Grid Engine (SGE).


Short Finder
Short Finder component added to PowerDRC/LVS

Short Finder is a special utility for graphical LVS debug purposes.
It delivers the following functionality:
  • Suggests a short location
  • Shorted net polygons in a table format
  • Allows to assign label for selected polygon
  • Allows to mark a polygon as 'deleted'
  • Recalculates the shortest path
  • Interactive work in KLayout editorc

KLayout integration
A large number of developers as well as our customers use KLayout editor so POLYTEDA integrated PowerRDE with KLayout.

PowerRDE integration with KLayout viewer and editor is available since PowerDRC/LVS release 1.7 and enables the user to:
  • Invoke PowerDRC/LVS from KLayout
  • Review results and highlight errors in KLayout
  • Find and highlight shorted nets using POLYTEDA Short Finder utilit
Power RCX
PowerDRC/LVS allows for extraction of parasitic capacitances with high degree of accuracy.

The supported input formats include GDS, OASIS or OpenAccess for layout, and CDL, SPICE, or VERILOG for schematic netlist.
In PowerDRC/LVS one and the same engine is used to run DRC, LVS, and RCX, so to run parasitic extraction you may use either a dedicated rule deck or an extraction rule deck with RCX rules. However, running RCX requires a separate license.
PowerRCX results correlate with proven in silicon on the following processes:
  • IHP SG13S 130nm
  • IHP SGB25V 250nm
  • TSMC CL018 and 152G 180nm (with shrink 0.84)

Fill layers generation
Running PowerDRC on a special fill rule deck results in generating of output.gds file with fill layers. The developer may attach these layers later as a separate group to some cell/top cell (hierarchically) using a layout editor.

Fill operation creates layers filled with specified rectangles at certain distance with or without offsets, either inside or outside the layer. Filling also may be done with a cell that contains arbitrary shapes in several different layers.
Why choose us?
Accuracy
Natively Flat Design that delivers superior accuracy compared to current high-end PV tools
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High Speed
PowerDRC/LVS is an efficient and innovative cloud-ready tool for physical verification of integrated circuits covering principal DRC and LVS tasks both in single- and multi-CPU modes that delivers super high speed
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Compatibility
Supports GDS, OASIS, and OpenAccess layout formats natively, Netlist SPICE, Verilog for LVS, ADS format when integrated with Keysight ADS
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Fast technical support
We have a team of qualified technical specialists that ready to help you
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Partners
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We will contact you within 12 hours